Current radio frequency (RF) receiver integrate circuits (ICs) often convert analog signals associated with a receive channel to digital data and then perform digital processing on this digital data. As part of this digital processing, digital clocks are utilized to operate the digital processing blocks. These digital clocks, however, can generate undesirable on-chip noise and interference within the broadcast channels being received. Where the channel to be received is known, frequency planning can be used to adjust digital clock frequencies among a number of specific clock frequencies such that interfering harmonics fall outside the frequency range for the channel to be tuned. However, where multiple channels are to be tuned from one or more frequency bands, this frequency planning becomes extremely difficult to implement due to the number of possible combinations of channels to be received.